The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-channel and n-channel field-effect transistors (nFETs and pFETS) that are coupled to implement logic gates and other types of circuits, such as switches. Field-effect transistors generally include an active semiconductor region, a source, a drain, and a gate electrode. When a control voltage exceeding a threshold voltage is applied to the gate electrode, an inversion or depletion layer is formed in a channel defined in the active semiconductor region between the source and drain by the resultant electric field, and carrier flow occurs between the source and drain to produce a device output current.
In a typical replacement metal gate process, sacrificial gate structures are used for forming a self-aligned gate-to-source/drain structure. The sacrificial gate structures are removed and replaced with a gate structure that includes a desired gate dielectric and gate electrode. In a gate-last process, gate height control is relevant to proper transistor function because variations in gate height may lead to measurable transistor performance variability. During reactive ion etching used to pattern a hardmask for a gate cut and subsequent reactive ion etching to remove the sacrificial gate structures at the location of the gate cut, an interlayer dielectric layer comprised of silicon dioxide and surrounding the sacrificial gate structures is exposed to the etching process. Due to poor etch rate selectivity, the interlayer dielectric layer may be recessed relative to the sacrificial gate structures at the location of the gate cut. Chemical mechanical polishing is used to expose the sacrificial gate structure for subsequent removal and also used to remove excess final gate fill metal after the replacement gate structure is finished. An inability to exert control over the CMP process must result in an inability to control the final gate height and introduces topography due to recessing of the interlayer dielectric surrounding the sacrificial gate structures.
Improved structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures are needed.